Classification of different processes in semiconductor manufacturing在半导体制造业中，各种不同的工艺的分类

在半导体制造业中，各种不同的工艺通常分为四大类：沉积、移除、图案结构、改变电气性能。

沉积是一种在晶片上生长、覆盖或转移材料的工艺。可用的技术包括物理气相沉积、化学气相沉积、电化学沉积、分子束外延以及最新的原子层沉积。

移除是一种去除晶片上材料的工艺，其中包括刻蚀工艺（干法或湿法）以及抛光。

图案结构是塑造或改变堆积的材料，通常被称为光刻。例如，传统的光刻技术，晶片涂上一层光刻胶，利用设备进行聚焦、对中、移动掩板，在短波光下完成光刻；用显影剂冲走暴露区域的光刻胶。在刻蚀或其他工艺后，利用等离子刻蚀机。

改变电气性能历来是用掺杂晶体管源（最初由扩散炉，后来通过离子注入）。这些掺杂工艺通过扩散炉退火，或用先进的设备进行快速退火实现；退火是为了激活植入的掺杂物。改变电气性能现在也延伸到通过低绝缘体暴露在紫外线工艺降低材料的介电常数。

现代芯片有多达11种金属生产水平，超过300道工艺处理步骤。

前道工艺过程

前道工艺是指在硅上形成晶体管。原始的晶片是由高纯度生长而来，实际上通过外延硅层几乎没有缺陷。在最先进的逻辑器件，硅外延步骤之前，执行技巧提高晶体管的性能。其中一个方法是引入一个硅变体，如硅锗沉积。一旦外延硅沉积，晶格拉伸，从而提高电子迁移率。另一种方法称为绝缘硅技术，是在原始硅片与硅外延薄层之间插入绝缘层，该方法导致减少寄生效应晶体管的创建。

Gate oxide and implants

栅氧化和注入

前端表面工程后续的工艺是增长闸极介电层(传统的二氧化硅)，门的模式，源和消耗区域的模式，以及随后的植入或掺杂物扩散获得所需的互补的电气性能。在动态随机存取记忆体(DRAM)器件中，存储电容也被组装，通常堆放存取记忆体上面(现已倒闭的DRAM制造商奇梦达)实现了将这些电容器嵌入到硅表面刻蚀槽)。

后道工艺过程

金属化：一旦各种半导体器件被生产,它们必相互连接形成所需的电路。这一系列的工艺步骤被统称为后道工艺（不要与封装和测试阶段混淆）。后道工艺过程包含创建被介电层隔离的金属线。绝缘材料通常用二氧化硅或硅玻璃，尽管芯片制造商提供的材料介电常数低于2.2，但是近来低介电材料被使用（例如硅碳氧化物），典型的介电常数为2.7（二氧化硅是3.9）。

互连

一个标准电池通过四层平面型铜导线互连，下至多晶硅(粉红色)，井(灰色)和基质(绿色)。

以前，金属线都是铝制的。首先沉积一层铝层，经过光刻、刻蚀，留下铝线，然后绝缘材料覆盖裸露的铝线。不同的金属层利用绝缘材料上的蚀孔（称为“贯穿孔”）相互连接，通过化学气相沉积技术将钨沉积到贯穿孔中；这种方法还应用于很多内存芯片制造中，例如动态随机存取存储器(DRAM)，因为其互连的数量级别很小（目前不超过四）。

近年来，随着逻辑器件增加大量的晶体管，互连数量级别也大大增加，以至于如今使用微处理器互连，线路的时间延迟变得如此重要,以至于需要改变布线材料(从铝到铜)，以及介质层材料的改变(从二氧化硅到新的低绝缘体)。这种性能的提高，同时也通过金属镶嵌工艺降低了成本，减少了工艺步骤。随着互连数量级别的增加，需要整平前层以确保后续前平面光刻。缺少这个步骤，水平面会越来越弯曲，影响光刻外延，从而干扰光刻的能力。尽管当互连数量级别不超过三时，依然适用干法刻蚀处理，但抛光是实现平整的主要处理方法。

晶圆测试

晶片的高度序列化性质工艺处理增加了不同工艺步骤间的计量需求。晶圆测试计量设备用于验证晶片在测试之前的工艺过程中没有损坏；如果在一个晶片有太多的晶粒不合格，整个晶片将报废，降低后续工艺成本。

器件测试

一旦前道工艺完成，半导体器件会经过各种各样的电气测试,以确定她们是否能够正常工作。产品的合格率直接影响到制造商的收益，制造商对他们的收益率通常是保密的，但它可以低至30%。

半导体生产线利用电子测试仪，通过压在晶粒上的探针，对芯片进行测试，测试仪器对不合格的芯片打点做标记。目前, 根据预定的测试范围，通过电子染料标记功能，将中央计算机储存的数据筛选出来(即分为虚拟垃圾箱)。最终根据筛选的数据绘制成一张晶粒分布图，用来跟踪和标记不合格的芯片。这张晶粒分布图还可以使用在晶片组装和封装上。封装后的芯片同样需要测试，防止导线断路或模拟性能改变，这被称为“最终测试”。

通常，工厂测试的成本费用每秒几分钱。测试时间从几毫秒到几秒，通过优化测试软件来减少测试时间。因为许多测试人员有足够的资源来执行大部分或所有的同步测试，多个芯片(多站点)测试也是可行的。

芯片的设计常常有“测试性特征”如扫描链或“自检“功能快速测试，以降低测试成本。在某些使用专门的模拟工厂工艺的设计中，测试期间通过激光微调，以实现预期的、紧密分布的阻值。

良好的设计会测试和用统计学的方式测试极限性能(在高温状态下以及极端的工艺条件测试硅的极限性能)。大多数设计至少应对64种极限状态。

晶粒准备

测试后，通常需要经过减薄后再将晶片拆分、划分晶粒，这一过程称为晶片切割。只有好的，无划痕的芯片才进行封装。

封装

塑料或陶瓷封装包括晶粒装配、焊接晶粒与封装外壳上的引脚以及晶粒密封。细小的导线用来连接引脚和晶粒。以前是通过手工焊接导线，如今使用专用的机器代替。传统上，这些导线由黄金构成，通向使用镀锡的铜“引线框”；而铅是有毒的，因此无铅“引线框”现已被RoHS强制使用。

另一种封装技术--芯片级封装。如同大多数封装，塑料双列直插式封装体积比实际的晶片大很多倍，而芯片级封装芯片尺寸与晶粒大小几乎一致；在划片前，芯片级封装外壳就可以设计出来。

封装后芯片需要测试以确保在封装过程中未被破坏、晶粒与引脚间的连接正确。然后在封装外壳上用激光标记芯片的型号。

     In the semiconductor manufacturing industry, different processes are usually divided into four categories: deposition, removal, pattern structure, change of electrical performance. 

    Deposition is a process of growing, covering or transferring materials on a wafer. Available techniques include physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy and the latest atomic layer deposition. Removal is a process of removing material from a wafer, including etching (dry or wet) and polishing. 

   Pattern structure is to shape or change the accumulation of materials, usually known as lithography. For example, in the traditional lithography technology, the wafer is coated with a layer of photoresist, focusing, centering and moving the mask with the equipment, and the lithography is completed under the short wave light; the photoresist in the exposed area is washed away with the developer. After etching or other processes, plasma etching machine is used. 

   The change of electrical performance has always been made by doping transistor source (initially by diffusion furnace, later by ion implantation). These doping processes are realized by diffusion furnace annealing or rapid annealing with advanced equipment; annealing is to activate implanted dopants. The change in electrical properties now extends to the reduction of the dielectric constant of the material through a process of low insulator exposure to ultraviolet light. Modern chips have up to 11 metal production levels, more than 300 process steps. 

   The former process refers to the formation of transistors on silicon. The original wafer is grown by high purity, and there are almost no defects in the epitaxial silicon layer. Prior to the most advanced logic device, silicon epitaxy step, execution techniques improve transistor performance. One way is to introduce a silicon variant, such as SiGe deposition. Once the epitaxial silicon is deposited, the lattice is stretched to improve the electron mobility. Another method, called insulating silicon technology, is to insert an insulating layer between the original silicon wafer and the silicon epitaxial thin layer, which leads to the reduction of the creation of parasitic effect transistors. 

  The subsequent process of gate oxide and implants gate oxidation and injection front-end surface engineering is to grow gate dielectric layer (traditional silica), gate mode, source and consumption area mode, and then implant or dopant diffusion to obtain the required complementary electrical performance. In dynamic random access memory (DRAM) devices, storage capacitors are also assembled, which are usually stacked on the memory (Qimonda, the now bankrupt DRAM manufacturer), to embed these capacitors into the silicon surface etching groove). 

Metallization: 

once various semiconductor devices are produced, they must be connected to form the required circuit. This series of process steps are collectively referred to as post process (not to be confused with the packaging and testing phases). The latter process involves the creation of wires isolated by a dielectric layer. Silicon dioxide or silicon glass are usually used as insulating materials. Although the dielectric constant of materials provided by chip manufacturers is lower than 2.2, recently low dielectric materials (such as silicon carbon oxide) are used, and the typical dielectric constant is 2.7 (silicon dioxide is 3.9). 

Interconnection a standard battery is interconnected by four layers of flat copper conductors down to polysilicon (pink), well (grey) and substrate (green). Before, the wires were made of aluminum. First, a layer of aluminum is deposited. After photolithography and etching, the aluminum wire is left, and then the insulation material covers the exposed aluminum wire. Different metal layers are interconnected by etched holes (called "through holes") on the insulating material, and tungsten is deposited into the through holes by chemical vapor deposition technology; this method is also applied to many memory chip manufacturing, such as dynamic random access memory (DRAM), because the number level of interconnection is very small (currently no more than four). 

In recent years, with the increase of the number of transistors and the level of interconnection, the time delay of the circuit becomes so important that the wiring materials (from aluminum to copper) and the dielectric layer materials (from silicon dioxide to new low insulator) need to be changed. The improvement of this property also reduces the cost and process steps through the metal inlay process. As the number of interconnects increases, the front layer needs to be flattened to ensure the subsequent front plane lithography. Without this step, the horizontal plane will become more and more curved, affecting the lithography extension, thus interfering with the lithography ability. Although dry etching is still applicable when the number of interconnections is no more than three, polishing is the main method to achieve flatness.

       The high serialization processing of wafer test wafer increases the measurement demand between different process steps. Wafer test and measurement equipment is used to verify that the wafer is not damaged in the process before the test; if there are too many unqualified grains in one wafer, the whole wafer will be scrapped and the subsequent process cost will be reduced. 

     Once the device test is completed, the semiconductor devices will go through various electrical tests to determine whether they can work normally. The qualified rate of products directly affects the manufacturer's earnings. The manufacturer usually keeps their earnings secret, but it can be as low as 30%. The semiconductor production line uses the electronic tester to test the chip through the probe pressed on the grain, and the tester marks the unqualified chip. 

    At present, according to the predetermined test range, through the electronic dye marking function, the data stored in the central computer is screened out (i.e. divided into virtual dustbins). Finally, according to the selected data, a grain distribution map is drawn to track and mark the unqualified chips. This grain distribution map can also be used for wafer assembly and packaging. The packaged chip also needs to be tested to prevent wire breaking or analog performance changes, which is called "final test". Usually, the cost of factory testing is a few cents per second. Test time is from a few milliseconds to a few seconds. Test time is reduced by optimizing test software. Because many testers have enough resources to perform most or all of the synchronous tests, multi chip (multi site) testing is also feasible. The design of chips often has "testability" features such as scan chain or "self check" function to test quickly, so as to reduce the test cost. In some designs that use specialized simulation plant processes, the resistance values are achieved by laser fine-tuning during testing to achieve the expected, closely distributed values. A good design will test and statistically test the ultimate properties of silicon (at high temperature and under extreme process conditions). Most designs deal with at least 64 limit states. After the grain is ready for testing, it is usually necessary to separate and divide the wafer after thinning. This process is called wafer cutting. Only good, scratch free chips can be packaged. Package plastic or ceramic package includes grain assembly, welding grain and pin on package shell as well as grain sealing. Small wires are used to connect pins and grains. Previously, wires were welded by hand, but now they are replaced by special machines. Traditionally, these wires are made of gold, leading to tinned copper "lead frames"; lead is toxic, so lead-free "lead frames" are now mandatory by RoHS. Another packaging technology -- chip level packaging. Like most packages, the volume of plastic dual in-line package is many times larger than the actual chip, and the chip size of chip level package is almost the same as the grain size; before slicing, the chip level package shell can be designed. After packaging, the chip needs to be tested to ensure that it is not damaged during the packaging process and the connection between grains and pins is correct. Then the model of the chip is marked by laser on the packaging shell.